1. Field of the Invention
The present invention relates to the biasing of a mixer. More specifically, the present invention relates to the biasing of switches of a mixer having a variable quiescent current.
2. Description of the Related Art
FIG. 1 illustrates the simplified diagram of a mixer intended for shifting the frequency of an oscillating voltage signal IF. The mixer receives signal IF in a first stage or input stage 10. Input stage 10 has a transconductance function. It converts input voltage signal IF into a current signal IFxe2x80x2 and enables setting the quiescent current of the mixer. Current signal IFxe2x80x2 is provided by input stage 10 to a second stage 20.
Second stage 20 is a frequency shift stage or switch stage. It has the function of mixing, that is, of multiplying, current signal IFxe2x80x2 by a shift order LO. Shift order LO is a periodic voltage signal. Output signal RF has a frequency which is shifted with respect to input signal IF having the frequency of order LO.
For example, in telecommunication applications, and more specifically in the transmit portion of a mobile phone, signal IF is a signal having a frequency on the order of 200 MHz while shift order LO is a signal having a frequency on the order of 2 GHz. Output signal RF is for example the signal transmitted by a mobile handset to a fixed station.
It is further considered that, in the type of mixer shown in FIG. 1, the quiescent current is negligible. To modify the quiescent current of the mixer then enables modifying its gain, its linearity, and its electric consumption.
FIG. 2 illustrates the conventional forming of a mixer of the type previously described in relation with FIG. 1.
Input stage 10 includes an NPN bipolar transistor T1. Input signal IF is applied to the base of transistor T1 via a capacitor CF. The collector of transistor T1 provides output stage 20 with current signal IFxe2x80x2 (output signal of input stage 10). The biasing of transistor T1 is ensured by the connection of the base of transistor T1 to a block formed of a current source 11 and of a comparator 12, the operation of which is described hereafter. The emitter of transistor T1 is connected to a reference low supply rail (ground) via a resistor RE. The current control is made possible by a feedback loop including a comparator 12. The output of comparator 12 is connected to the control terminal of current source 11. An inverting input (xe2x88x92) of comparator 12 is connected to a terminal of a voltage source (VG) 13. The second terminal of voltage source 13 is connected to the circuit ground. The non-inverting input (+) of comparator 12 is connected to the emitter of transistor T1. Current source 11 typically is a P-channel MOS transistor P1. The source and the substrate of transistor P1 are connected to a high supply rail Vdd of the circuit. The drain of transistor P1 forms the output of current source 11 and is connected to the base of transistor T1. The gate of transistor P1 forms the control terminal of source 11 and is connected to the output of comparator 12. Then, the current of the mixer is determined by the copying of value VG of current source 13 across resistor RE. The value of this current thus is iE=(VG/RE). The value of voltage VG is determined by a control circuit not shown. For example, in mobile telephony applications, the choice of value VG depends on the level of the RF signal received by a fixed station (not shown).
Output stage 20 is a differential stage including a pair of NPN-type bipolar transistors, TN and TP. Transistors TN and TP will be placed close to each other to exhibit similar operating characteristics. The emitters of transistors TN and TP receive output signal IFxe2x80x2 of input stage 10. The emitters of transistors TN and TP are interconnected to the collector of transistor T1. A first shift order LON is sent to the base of transistor TN via a capacitor CN. A second shift order LOP, corresponding to first order LON with a 180xc2x0 phase shift, is sent to the base of transistor TP via a capacitor CP. The collectors of transistors TN and TP form the outputs of stage 20 and provide differential current signals RFN and RFP.
Transistors TN and TP are biased by the connection to a same biasing node 14 via respective biasing resistors RN and RP of same value. The value of the voltage at biasing node 14 is determined by a biasing network 15. Network 15 is formed by the series connection, between high power supply Vdd and the ground, of a constant current source S, of a resistor R0 and of two diodes D1 and D2. Diodes D1 and D2 are connected to enable flowing of a current from source S to the ground. Node 14 is connected to the intermediary node between source S and resistor R0. Diodes D1 and D2 have the object of reproducing in biasing network 15 the base/emitter voltage drops of transistors T1 and TN (in parallel with identical transistor TP). Resistor R0 has the object of reproducing in biasing network 15 the voltage drops across biasing resistors RN and RP and across resistor RE.
A disadvantage of the mixer of FIG. 1 is the impossibility of precisely knowing and controlling the level of the D.C. biasing of the bases of transistors TN and TP of output stage 20. The biasing level, that is, the voltage on the bases of transistors TN and TP, will vary on the one hand from one circuit to another and, on the other hand, during operation. Indeed, the biasing level varies according to the current level and variations.
On the one hand, the required biasing currents vary from one circuit to another due to the variation of parameter xcex2, that is, of the ratio between the current transmitted by a bipolar transistor and the control current, due to technological manufacturing dispersions. However, the three transistors TN, TP, and T1 of the circuit are formed simultaneously and substantially have the same parameter (that is, xcex2=iE/iB=iEN/iN iEP/iP, with the notations of FIG. 2). Typically, parameter xcex2 varies by a factor four in a range from 50 to 200.
On the other hand, for a given circuit, the current varies during operation according to the value VG selected by source 13 of input stage 10.
Whatever the origin of the current variation, it affects biasing currents iN and iP of transistors TN and TP of output stage 20. This variation causes a current variation in network 15. This current variation then causes a variation of the voltage across resistor R0 and thus of the voltage at biasing node 14. This results in a possible saturation of one or the other of stages 10 or 20.
In practice, the biasing of stage 20 must be known and controlled with a great precision to guarantee, independently from current variations:
a sufficiently low biasing for the two transistors TN and TP of the differential pair of output stage 20 not to saturate; and
a sufficiently high biasing to avoid saturation of transistor T1 of input stage 10 due to too low a collector/emitter voltage.
These problems are particularly enhanced and saturation phenomena are particularly frequent in the case of cells with a low supply Vdd, for example, on the order of 2.7 V.
In practice, the state of the art, to guarantee that transistor T1 of input stage 10 does not saturate, uses a current source S, the provided current of which has a high value. This value will be chosen according to the worst possible case in terms of current, that is, the case in which parameter xcex2 is very small while current iE (set by voltage VG) is maximum. For example for an emitter current iE of transistor T1 of input stage 10 having a value ranging between 1 and 5 mA, source S will have to provide a current (iEmax)/(xcex2min)=5*10xe2x88x923/50=100 xcexcA. As previously discussed, this causes risks of saturation of output stage 20. For example, for a parameter xcex2 of average value and for a current iE having a value on the order of 1 mA, it would be enough for source S to provide a 10-xcexcA current.
The present invention thus aims at providing a mixer having a controllable biasing.
The present invention aims at providing such a mixer, the biasing level of which remains steady during mixer operation.
The present invention also aims at providing such a mixer having a biasing level which is steady from one circuit to another, that is, whatever the parameter xcex2 of its transistors.
To achieve these objects, the present invention provides a mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, wherein a biasing network of the output stage includes, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.
According to an embodiment of the present invention, the input and output elements of the current mirror of the biasing network of the output stage are P-type MOS transistors.
According to an embodiment of the present invention, the stage of input of the signal to be shifted is a stage with a variable quiescent current.
According to an embodiment of the present invention, the biasing network includes between the biasing node and a circuit ground the series connection of a resistor and of two diodes, the diodes being connected to enable flowing of a current from the biasing node to the circuit ground.
According to an embodiment of the present invention, the constant current source includes a circuit of bandgap type adapted to ensuring a constant voltage across the resistor of the biasing network.
According to an embodiment of the present invention, the high supply of the mixer is a low-voltage supply.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.